Design Verification Engineer

Location: Bangalore, Doha

Type: Full-Time | Hybrid possible

Start Date: Immediate

 

Job Description

 

Summary

Do you enjoy working in a creative, engaging, and entrepreneurial environment? We place high value on our teams and are committed to pursuing excellence for all our partners.

SilTest provides state-of-the-art semiconductor engineering, test and qualification services to customers around the world. We do that by creating practical, high-quality solutions that help semiconductor product developers bring ideas from concept to mass production efficiently and cost-effectively.

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Our fast-growing team is looking for experienced Design Verification Engineers who can build robust verification environments, drive coverage closure and help ensure that complex semiconductor designs are functionally correct before tape-out.

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Typical Job Responsibilities:

If you tick more than half of these, you should consider talking to us.

 

• Create verification strategies and test plans from architecture, design specifications and product requirements.

• Develop reusable SystemVerilog/UVM testbenches, agents, monitors, scoreboards, checkers and coverage models.

• Build constrained-random and directed tests for IP, subsystem and SoC-level verification.

• Define and close functional coverage, code coverage and assertion coverage against agreed verification goals.

• Write, review and debug SystemVerilog Assertions and use formal verification where suitable.

• Integrate protocol VIPs and develop verification components for standard and proprietary interfaces.

• Debug RTL/testbench failures, waveform mismatches, coverage holes, regression failures and corner-case issues.

• Collaborate with RTL design, architecture, DFT, firmware and physical implementation teams to resolve issues early and systematically.

• Automate regressions, triage, reporting and verification dashboards to improve speed and repeatability.

• Train others on what you learned..

 

 

Requirements

Key Qualifications

 

• 5 to 10 years of hands-on design verification experience for semiconductor IPs, ASICs or SoCs.

• Strong SystemVerilog and UVM experience, including testbench architecture, sequences, scoreboards, coverage and reusable components.

• Good understanding of digital design fundamentals, RTL behavior, clocking, reset, low-power design and SoC integration concepts.

• Experience with coverage-driven verification, constrained-random verification, directed testing and regression management.

• Experience with assertions, functional coverage, code coverage, debug tools and waveform analysis.

• Knowledge of one or more standard interfaces or protocols such as AMBA AXI/AHB/APB, PCIe, Ethernet, USB, MIPI, memory interfaces, SPI, I2C or UART.

• Scripting skills in Python, Tcl, Perl or shell scripting for automation, regression control and reporting.

• Experience with major simulation and verification tool environments from Siemens, Synopsys or Cadence is a plus.

• Excellent communication in English and the ability to work in a multicultural, international team.

• A can-do attitude, structured debugging discipline and willingness to mentor others.

 

Benefits

What we offer

 

• A competitive compensation package

• A lucrative equity award

• Flexible work arrangement, hybrid or work from home, depending on the role

• Paid training at all levels

• Opportunity to work in an entrepreneurial environment and shape the future of the industry