Design For Test (DFT) Engineer

Location: Bangalore, Doha

Type: Full-Time | Hybrid possible

Start Date: Immediate

 

Job Description

 

Summary

Do you enjoy working in a creative, engaging, and entrepreneurial environment? We place high value on our teams and are committed to pursuing excellence for all our partners.

SilTest provides state-of-the-art semiconductor engineering, test and qualification services to customers around the world. We do that by creating practical, high-quality solutions that help semiconductor product developers bring ideas from concept to mass production efficiently and cost-effectively.

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Our fast-growing team is looking for experienced DFT Engineers who can work across IP and SoC-level testability, from DFT architecture and implementation through ATPG, coverage closure, silicon bring-up support and production debug.

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Typical Job Responsibilities:

If you tick more than half of these, you should consider talking to us.

 

• Define and implement DFT requirements for new IPs, subsystems and SoCs in alignment with design architecture, product requirements and test strategy.

• Work on scan architecture, scan insertion, test compression, MBIST/LBIST integration, JTAG/IJTAG access, boundary scan and on-chip clock control where applicable.

• Run DFT rule checks, testability analysis, scan stitching validation, ATPG setup, pattern generation, pattern validation and coverage closure.

• Analyze coverage gaps, untestable faults, X-sources, pattern count, test power and test-mode constraints, then drive practical closure actions with design and verification teams.

• Create and review DFT specifications, test mode definitions, constraints, integration guidelines and sign-off checklists.

• Collaborate with RTL design, verification, physical design, product engineering and ATE teams to ensure DFT intent is preserved through implementation and silicon test.

• Support silicon bring-up, pattern correlation, diagnostics, failure analysis and production issue debug.

• Develop scripts and automation to improve DFT implementation quality, regression execution, reporting and repeatability.

• Contribute to methodology improvement, reusable flows, documentation and internal training.

• Train others on what you learned.

 

 

Requirements

Key Qualifications

 

• 4 to 10 years of hands-on experience in DFT implementation, ATPG, DFT verification or silicon test support.

• Strong understanding of scan, ATPG, test compression, MBIST, JTAG/boundary scan and fault models.

• Experience with one or more major DFT/ATPG tool environments such as Siemens Tessent, Synopsys TestMAX/DFT Compiler/FastScan or Cadence Modus.

• Good RTL knowledge in Verilog/SystemVerilog and practical understanding of SoC integration, clocking, reset, low-power and timing constraints.

• Ability to debug DFT rule violations, coverage limitations, simulation mismatches, pattern failures and silicon correlation issues.

• Scripting skills in Tcl, Python, Perl or shell scripting for automation and flow development.

• Knowledge of semiconductor product development lifecycle from concept through silicon bring-up and production release.

• Excellent communication in English and the ability to work in a multicultural, international team.

• A can-do attitude, engineering discipline and willingness to share knowledge with the wider team.

 

Benefits

What we offer

 

• A competitive compensation package

• A lucrative equity award

• Flexible work arrangement, hybrid or work from home, depending on the role

• Paid training at all levels

• Opportunity to work in an entrepreneurial environment and shape the future of the industry